Unified Power Quality Conditioner Engineering Essay

Unified occasion Quality Conditioner Engineering EssayAbstract-The aim of this paper is to present a aeonian absolute frequency integrate indicator lineament conditioning dodging(CFUPQC)which consists of an unified ply quality conditioner(UPQC) extended by adding a frequency changer in amidst the shift expeditious filter and serial diligent filter . The series active filter and shunt active filters mainly use to compensate the emf, up-to-the-minute imbalance and good-hearteds. The frequency converter is used to compensate the come forth frequency when it varies beyond the role quality limit. The proposed configuration any converters be connected back to back on the dc side and share the common dc link capacitor. The show allow fors are presented to confirm that the new approach has better performance than the traditional UPQC. force Terms-CFUPQC, frequency changer, potency informant converter (VSC), Matlab simulinkINTRODUCTIONUunifed power quality conditione r is an advanced concepts in the area of power quality control. The basic do working regulation of unified power quality conditioner is based on series and parallel power converters that share a common dc link 1.Unified power quality conditioner is used to compensate voltage sag, voltage swell 2 , current harmonics 3 it is also cooks an impact on the reactive power 4 through shunt voltage source inverter and series voltage source inverter. In roll to avoid the switching oscillation, a passive filter is applied at the output of each inverter. At the output of shunt inverter a high pass second mark LC filter is allocated and the output of series inverter low pass second order LC reverberance filter is allocated. UPQC controller provides the compensation voltage through the UPQC series inverter and conditioning the current through the shunt inverter by instantaneous sampling of effect current and source voltage. The reference current are compared with the shunt inverter output c urrent (,) and are fed to hysteresis type(PWM) current controller. There are some problems with PQC. As the fork out frequency changes the UPQC will noncompensate the voltage sag and swell and current harmonicsproperly. This happens due to the presence of LC filters at theInverters output terminals. It is directly alter by the mutation of supply frequency.Fig.1 Basic Configuration of Constant Frequency Unified Power Quality Conditioner (CFUPQC)Fig 1 shows the proposed improved configuration of unvaried Frequency unified power quality conditioner. This modified unified power quality conditioner concepts enables the PWM converter to perform not only active filtering finding, also the lean of frequency changer. The compensation principle of the CFUPQC will be described in the coming sections. The proposed unified power quality conditioner has to satisfy the following requirements. Reactive power is well-kept at minimum value. The alloy voltage should be maintained at the rated supply voltage. Maintain the input current with very low harmonic content. Assure the supply frequency is permissible within the power quality limits .The simulations result will be presented to validate the proposed CFUPQC.frequency quality indicesIn order to characterize the power system frequency chthonian normal operating condition the following indices are usedWhere fr is the rated frequency (50 or 60) Hz and f is the palpable frequency.The relative frequency deviation(2)The integral deviation during the delay needful to ensure appropriate of clock synchronized to the electrical vane frequency(3)According to the standard En 50160/2006rated frequency of supply voltage is 50Hz.Under normal operation conduction the mean value of the fundamental frequency heedful over loss stay within the following range.50 Hz+ 1%.ie 49.5-50.5Hz for 99.5%of the year50 Hz+ 4%.ie 47-52Hz for 100%of the time.But as power frequency may not be exactly 50Hz within the time interval. The fundamental f requency output is the ratio of the number of integer bicycle counted clearing 10s time interval divided by the cumulative value of the integer value. The step taken to maintain the frequency with in necessitate limits fabricate deviation from the normalized value very rate phenomena. In this way an analysis is of the influence of frequency variation on the final customer is only for a reduced interval about +3Hz of the rated value and for rather short period. Within the reduced variation field (40%)a considerable number of static customers are not affected by the system variation(rectifier , resistance, ovens, electric arc ect)but 60%of the consumers (fans, motors ect)affected by the frequency variations. The asynchronous and synchronous driving motors connected the supply network used extensely in individual acceleration have the power frequency changes. Depending on the mechanical characteristic speed of the motor and also depends on the supply frequency 13.The speed of asynch ronous motors or synchronous motor unlimited drags to the electric power supply variations s proportional to the applied voltage frequency. The frequency variation leads to the correspond modification of the process production time throughout the supply with a reduced frequency depressing the supply frequency capacitive circuit, transformer, relay coil are affectedConstant Frequency Unified Power Quality Conditioner (CFUPQC)CFUPQC structureFig.3 Proposed ConfigurationModified configuration of UPQC consist of shunt active filter, series active filter, voltage source inverter and voltage source converter shown in Fig(3).CFUPQC similar to the UPQC expect the frequency changing section. UPQC has the potential drawbacks in the crossing filtering performance. Since its filter in characteristics depends on freightage impedance and supply frequency. CFUPQC series active filter is used for compensation the voltage harmonics and voltage imbalance In addition the voltage source converter su pplies the AC to DC power and is fed to common DC link. The CFUPQC consists of parallel active filter (PAF) that eliminates load harmonics and compensates load reactive power. The control equation isIpf=G.IL (4)Where g is the control function, is fundamental frequency.IL is the load current, Ipf is the parallel filter input current components for compensation are extracted from load current and load voltages using theory while the converter is a current controlled device using 20 kHz clocked hysteresis band.Series active filter (SAF) that compensates supply harmonics flicker, voltage sag/swell, instability and diode + capacitor type load harmonics to flow in to the parallel filter. Control equation iscomp (5)Where k is regulator gain, Usf is the series filter voltage, Ish are harmonic supply current and Ucomp is compensation voltage needed to remove supply voltage imperfection. Ish are extracted to theory.Active rectifier (AR) for real power transfer to/from common DC bus and for D C bus control. Switching losses and power received from the dc link capacitors through the series inverter faeces decrease the average value of dc bus. Other distortions such as unbalanced conditions and sudden changes in load current can result in oscillation in dc bus voltage .In order to solve the fluctuated dc voltage the three pattern rectifier is used .DC bus voltage is maintained constant using three- form rectifier converter for bi-directional power flow and is controlled in such a way that it is insensitive to supply voltage imperfections.Rms value of the output voltage Vorms=0.9558VmlRms value of the output current Iorms=0.9558ImlWhere ml is maximum value of line current. Multi stage 48 pulse voltage source inverter (VSI) supplies the constant power frequency when the supply frequency will change. Here multilevel voltage source inverter is used, to eliminate the harmonic component of the output. The frequency converter is placed in between the series and shunt active fil ters. Normally the voltage source converters (rectifiers) generate the current harmonics. In order to avoid the harmonics and reactive power the rectifier is placed at the middle of the two active filters. Similarly if the load is increased voltage dip may occur in front of voltage source inverter. At the same time series active filter compensate the voltage problems.Control system of the CFUPQC shunt PartFig.4 Control System of the Shunt CFUPQC1) CFUPQC shunt inverter control systemIn the Fig (4) shows the shunt inverter controlling block diagram of CFUPQC using synchronous reference frame theory where the sensitive fill up current are . The measured currents of load are transferred in to frame using sinusoidal functions through synchronous reference frame renascence. The sinusoidal functions are obtained through the grid voltage using phase lock loop(PLL). Here the currents are divided in to ac and dc components(6)(7)The equation (6) and (7) and are the real and reactive compone nts.ac components and dc elements can be derived by low pass filter.are the dc components and are the ac components of . The control algorithm corrects the systems power factor and compensates all the current harmonica component by generating the reference currents given in equation= (8)= (9)The reference current is transferred in to frame through reverse conversion of synchronous reference frame. Resulted reference current () and the output current of shunt inverter () are fed to the hysteresis band controller. Now the required controlling pulses are generated and the required compensation current is generated by the inverter applying these signals to shunt inverters power switch gates.2) CFUPQC Series Inverter Control SystemFig.5 Control System of the Series CFUPQC2) CFUPQC series inverter control systemFig (5) shows the CFUPQC series inverter controlling block diagram using synchronous reference frame theory. In this method the desired value of load phase voltages in d axis and q axis is compared with the load voltage and the result is consider as the reference signal. The supply voltage detected is detected and transform in to the synchronous reference frame using(10)The compensating reference voltage in the synchronous reference frame is defined as(11)The compensating reference voltage in (11) is then transformed back into the reference frame .Resulted reference voltage () and the output current of shunt inverter () are fed to the hysteresis band controller. The required controlling pulses are generated and the required compensation voltage is generated.3) Control system of 48 pulse voltage source inverter48-pulse voltage source converter consists of four-spot three phase, 3-level inverters and 4 phase- slip transformers creating phase shift of +/- 7.5degree. This transformer setup neutralizes all odd harmonics up to 45th harmonic. Eight 6-pulse inverters are combined to obtain a 48-pulse with the purpose of reducing harmonic content. Table 1 shows the v alues of phase shifts which are applied to the inverter voltages in two steps, namely in firing pulses and in Zig-zag transformers, to create a 48-pulse swingform at the output .Table 148 Pulse voltage source InverterCoupling transformerGate pulse pattern pattern shifting transferY-Y+11.25-11.25-Y-18.75o-11.25oY-Y-3.75o+3.75o-Y-33.75o+3.75oY-Y+3.75o-3.75o-Y-26.25o-3.75oY-Y-11.25o+11.25o-Y-41.25o+11.25ocontent in the order of n= 48m1, where m= 0, 1, 2. The main-inverter intermediate-circuit capacitors together have an energy storage capacity of only 15 J/kVA. An output switching frequency of 1 kHz is chosen, which is fairly reasonable for this converter. Input is a frequency reference, which is passed through a rate limiter in order to be within the limits of maximum acceleration.Fig.6 Control System of the Frequency changer CFUPQCExcept for the 23rd and 25th harmonics, this transformer arrangement neutralizes all odd harmonics up to 45th harmonic. Y and D transformer secondarys can cel harmonics 7+12n (7, 19, 31, 43,)and 5+12n (5, 17, 29, 41,) .In addition, the 15 phase shift between the two groups (Tr1Y and Tr1D leading by 7.5, Tr2Y and Tr2D lagging by 7.5) that allows cancellation of harmonics 11+24n (11, 35,) and 13+24n (13, 37,). Considering that all 3n harmonics are not transmitted by the transformers, the first harmonics that are not canceled by the transformers are therefore the 23rd, 25th, 47th and forty-ninth harmonics. By choosing the appropriate conduction angle for the three-level inverter ( = 172.5), the 23rd and 25th harmonics can be minimized. Using a bipolar DC voltage, the voltage source inverter thence generates a 48-step voltage approximatly a sine wave. The secondary sides of the coupling transformers are connected in series to sum the output voltages of individual VSIs and results in a multi-pulse phase voltage which can be expressed mathematically as follow(12)Both equations (12) and (13) which are phase-to-phase and phase-to-neutral vol tage representations, respectively, show that harmonics up to 47th order are inherently filtered. The signalization of the 48-pulse inverter are generated for the inverter having -41.25 of gate pulse phase and directly fed to the corresponding inverter. PWM signals for the remaining inverters are obtained by applying relevant phase shifts to the set of PWM signals generated. For example, in order to obtain the pulses for the inverter having -11.25o of gate pulse +30o of phase shift is applied to the closed loop current controllers output. In practice, the phase shifting of the pulses is realized by applying a delay in the first cycle. The generated set of pulses is the earliest set appearing at the time-line and since it is not possible to apply a negative delay the earliest appearing set is generated and the rest are delayed accordingly. When the supply frequency is exceeded beyond the power quality limit the constant frequency voltage source inverter control system change the load from source power supply to the constant frequency inverter power supply.Simulation ResultsThe proposed system, simulation results is simulated by MATLAB software.Fig 7Current harmonic minimization when the supply frequency is normalIn the preceding(prenominal) simulation some capabilities of UPQC to solve power quality problems are shown. The nonlinear load which is produced harmonic current to the network. Fig. 7 shows that the shunt part of UPQC compensates these harmonicsComponents when the supply frequency is normal.Now assume that a deep and unbalance voltage sag, as occurs at t = 0.2 s to 0.25 s and voltage swell occurred 0.26 and lasts for 0.3 second.Fig.8. Sag swell condition when the supply frequency is normalIn Fig(8) the UPQC inject the compensation voltage via series inverter and compensate efficiently at 0.2 second sag condition and voltage swell condition at supply frequency normal (60Hz)Fig .9.Series UPQC when the frequency exceed the power quality limitIn fig 9 sh ows the operation of UPQC when the supply frequency exceeds the power quality limits the output was not found satisfactory .The supply beyond the power quality limit (greater than 63 Hz)at 0.25 second the load voltage waveform varies. The frequency increase rapidly the voltage waveform highly distorted as shown in the simulation results Fig 9.Based on the simulation result Fig 10 it is intended that if the supply frequency varies greater than power quality limit the load current wave form is distorted. If the frequency increases the wave form also distort rapidly as shown in fig10.Fig 10. CF- UPQC Operated when Frequency greater than the Power quality limitsFig 11. CF- UPQC Operated when Frequency greater than the Power quality limitsFig 11showsthe proposed CFUPQC model was simulated for a period of 0.01 sec to 0.5 sec from the results in fig 11, it was seen that at 0.28 sec the supply frequency cut through the power quality limit at 0.29.Fig.12. CF-UPQCs inverter supplying current under over frequency conditionThe above simulation shows the 48 pulse inverter carries the load current when the supply frequency varied beyond the power quality limit. When the frequency exceed the limits at 0.28 sec. the voltage source converter supply the power.The above simulation result Fig(13) clearly shows when the frequency changes the asynchronous motor speed also changes and the UPQC also not deliver the voltage sinusoidal. In this case the load connected in to paper mills, relays are affected.Fig.13. UPQC connected asynchronous motor under over frequency conditionFig.14. CFUPQC connected asynchronous motor under over frequency conditionThe proposed model simulation fig 14 shows when the supply frequency change the motor speed not changed and the CFUPQC also work satisfactoryTABLE I11PARAMETER VALUES OF THE UNDERPROPOSED SYSTEMPower quality problemsUPQCUPQCCF-UPQCCF-UPQCFrequency Hz58-62Hz62Hz-60-